1. Field of the Invention
The present invention relates to a semiconductor chip package structure, and more particularly, relates to a multi-chip package structure with multiple power connections.
2. Description of the Related Art
Due to the demand for small, lightweight and powerful electronic products, demand for multi-chip package (MCP) semiconductor chip package structures, to achieve requirements of multi-function and high performance, have increased. A conventional multi-chip package structure (MCP) integrates different types of semiconductor chips with different operating power requirements, for example, logic chips, analog chips, controller chips or memory chips, in a single chip package structure. Generally, for power requirements of the conventional multi-chip package structures (MCP), multi-power chips and corresponding input/output electrical connections of the package structures, for example, bonding pads or bonding wires, are used to provide different operating powers.
A power net of the conventional multi-chip package structure has a more complex layout because different operating powers are needed for the conventional multi-chip package structure. Therefore, a segment power net has been used, wherein the segment power net is disposed in the conventional multi-chip package structure, electrically connecting to the corresponding bonding pads. Next, the corresponding bonding pads of the conventional multi-chip package structure, is electrically connected to defined pins through a ball grid array (BGA) substrate. For the conventional multi-chip package structure, however, bonding pad positions, which respectively connect to the different operating powers, are fixed because positions of the corresponding segment power net is fixed. Thus, negatively increasing layout area of the bonding pads of the conventional multi-chip package structure. Additionally, using the BGA substrate for the conventional multi-chip package structure results in relatively higher fabrication costs.
Therefore, a novel semiconductor chip package structure with high integrated density and low fabrication costs is desirable.